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A Comparison of OpenVPX System Bandwidth Between Serial RapidIO® and 10 Gigabit Ethernet

May 02, 2011

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The VITA 65 (aka OpenVPX) specification has introduced a number of standardized backplane topologies. The major addition brought by VITA 65 is the standardization of systems that employ one or more centralized switch cards. For systems based on Ethernet, a central switch is the norm. For Serial RapidIO (SRIO), VITA 65 adds central switched architectures to the list of possible topologies that includes switch-less mesh implementations.

The cornerstone of the VITA 65 central switch topology is the 16-slot backplane with 14 payload cards and two switch cards. Known as BKP6-CEN16- 11.2.2-n, this is the maximum size backplane that accommodates 1"pitch cards (the de facto standard) within a 19"rack enclosure.

This paper compares the bandwidth available to processors resident on the payload boards using the CEN16 switched architecture for Serial RapidIO and 10 Gigabit Ethernet (10GbE). The analysis compares two different "benchmark"data flow models, the classic all-to-all case typical of a corner turn operation, and a pipeline case.

The analysis will show that the SRIO systems have more than three times greater bandwidth than 10GbE, and that half of that improvement is due to the more flexible routing afforded by actual hardware implementations that can be achieved with SRIO silicon.

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