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Wideband DDC as Part of an Integrated Approach

July 03, 2016 | BY: Jeremy Banks, Paul Garnett

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Digital Down Conversion (DDC) and its trends

As technology improves, “Direct Radio Frequency (RF)” has become the holy grail of RF systems. Instead of relying on analog tuners which see only a piece of the Radio Frequency spectrum, direct RF allows you to see the full spectrum of interest. Being able to digitize the RF directly removes the need for dual digitizers for both I and Q, enhances performance(e.g. no ADC matching), and delivers size, weight and power (SWaP) improvements. For the best narrowband at high frequency (>5-10 GHz) performance tuners (or analog down converters) are still dominant – but the trend higher band direct RF continues.

Figure 1a: Generic Wideband DDC

The Challenge

Wideband applications, especially in the multi-GHz range, have to deal with a large amount of unnecessary data, driving the need for multi-channel tuners. Despite this increasing shift towards digitization and faster processing, the amount of incoming data remains a burden; both in moving and processing it.

Techniques like Digital Down Conversion (DDC) are used to extract the frequency bands of meaningful data ready for processing. DDCs have become a staple over the years, and devices like Texas Instruments’ GC4016 (formally GrayChip) narrowband DDC became industry standard components. However, the increasing speed requirements to handle the greater volumes of data and higher channels densities has meant the DDC function has migrated into the domain of FPGAs, saving space while providing greater flexibility.

The Challenges of Direct RF Sampling

For all the advantages of direct RF sampling, there are also some challenges. Digitizing the data fire hose at RF speeds can include multiple channels. For example, 4 Gsps for first Nyquist sampling of the L-band frequency range at 12 bits resolution. This would result in a raw data rate of 6-8 GBps depending on whether data packing is an option. Moving such high volumes of data and processing in real-time is ideally suited to FPGAs, but despite the increasing size of FPGAs, simply handling these data rates can be a task in itself for even the most skilled FPGA developer.

Download our White Paper to read more about:

  • Digital Down Conversion (DDC) trends
  • The anatomy of DDCs
  • Challenges of Direct Radio Frequency sampling
  • Customizing DDCs
Jeremy Banks, ISR, embedded computing

Author’s Biography

Jeremy Banks

Product Marketing Manager, ISR Solutions

Jeremy Banks is a Product Marketing Manager for Sensor and I/O Processing in the ISR group at Curtiss-Wright. He has been involved in the defence embedded computing industry for over 25 years holding positions in engineering design, marketing and product management in DSP, Multi-Processing, RF IO, SBCs, FPGAs and System solutions. Jeremy is a graduate of the University of Surrey in Electronic and Electrical engineering.

Author’s Biography

Paul Garnett

Systems Architect

Paul Garnett is the System Architect in the UK Systems Engineering team at Curtiss-Wright. His 30 year career in electronics has encompassed design and architecture of SBCs, fault-tolerant computers, rugged embedded systems for MIL/Aero, high speed data acquisition and FPGA signal processing. Paul is a graduate of Imperial College, London with a Master's degree in Computer Science. He holds 73 US patents.

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