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FMC standard benefits high-speed FPGAs in aerospace and defense

October 05, 2010 | BY: Jeremy Banks

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New generations of FPGAs present developers with a level of processing performance and potential I/O bandwidth that cannot easily be matched by conventional CPU configurations. While many COTS solutions enable developers to readily make use of FPGAs for processing, the real challenge to an application is often measured in terms of I/O bandwidth, latency and connectivity. For example, military electronic counter-measures (ECM) applications require high bandwidth data input, processing and data output with minimum latency. The FPGA mezzanine card (FMC) (ANSI/VITA 57.1) directly addresses the challenges of FPGA I/O by solving the dual problem of how to maximize I/O bandwidth while still being able to change the I/O functionality. FMCs offer an elegant, simple solution because they only host I/O devices, such as ADCs, DACs or transceivers. FMC modules have no on-board processors or bus interfaces, such as PCI-X. Instead, FMC modules take advantage of the intrinsic I/O capability of FPGAs to separate the physical I/O functionality on the module from the FPGA board design of the host of the module, while maintaining direct connectivity between the FPGA and the I/O interface.

As recently as two or three years ago, leading off-the-shelf high-end ADCs could only achieve 1.5 to 3 Gbit/s bandwidth performance with 8-bit resolution. Since then, the performance of commercial ADC devices has increased dramatically. Today high-end ADCs are approaching 4 Gs/s bandwidth with 12-bit resolution. Earlier ADC technology was either not fast enough, or lacked the resolution, or both combined, to enable direct digital conversion of analog signals. This resulted in more cost and reduced performance because a system would typically require two RF heterodyne receiver front-ends to handle the down-conversion stage before the data got to the ADCs attached to the FPGAs. Today the function of FPGAs is as true processors that have large blocks of digital circuitry in which signal processing algorithms such as FFTs can be stored. FPGAs are very good at handling signal processing in the digital domain.

Nowadays faster, higher resolution ADCs have the ability to take an input signal at a microwave frequency and convert it at that frequency rather than requiring the use of a costly intermediary down converter. Higher end ADCs can sample at rates in excess of 3 to 4 gigasamples, which approaches the 1.5GHz L-Band and beyond. Sampling rates that exceed 1 GHz and faster now allow bandwidths of up to 500 MHz to be processed. And the higher bit-resolution of the new ADCs has increased system dynamic range, the span from the weakest to the strongest detectable signal that it can handle. These new high-resolution ADCs can sample at rates near 200 MS/s, and soon will reach 250 MS/s with 16-bit resolution. They can dramatically enhance the capabilities of wideband receivers by increasing their sensitivity and selectivity, which affects the system ability to intercept and characterize captured signals. The design challenge at these high data rates is how to interface these newly obtainable levels of resolution to the digital domain, a task that traditional processors cannot handle. The answer is a combination of baseboard FPGAs and FMC I/O cards. When combined with larger FPGAs and the new industry- standard FMCs, the new generation of ADCs enables system designers to integrate open standards-based board systems in which both ADC and DAC capabilities are directly coupled to the processing element, provided by the FPGA. The result is an order of magnitude improvement in latency from input to output. Even better for space, weight and power constrained embedded systems, the increased bandwidth of the new ADC devices does not come at the cost of a comparable rise in power consumption. We are seeing these devices with power dissipations rated near 2W per converter, which means that a quadchannel FMC will require less than 10W. The FMC (VITA 57) standard, recently approved by ANSI, provides a method for directly coupling FPGAs on the baseboard with I/O devices on the small mezzanine FMC board. FMCs enable the board bus structure to be bypassed, providing direct I/O to the FPGA processing element on the host card. This drastically improves data rates and reduces latency compared to designs where the I/O devices reside on the main PCB. Another advantage is that FMCs make it easier to tune a particular I/O need with a common processing engine, and to upgrade performance as newer and better I/O devices become available without a major baseboard redesign. The most popular mezzanine format for defense embedded computing is PMC which uses the PCI, and PCI-X. The newer XMC replaces PMC parallel PCI or PCI-X bus with a serial interface, of which the most common protocol support is PCI Express. Unfortunately, the throughput available from FPGAs is beyond the capabilities of PMC or XMC. FPGAs can be used to implement the necessary interfaces, so advantage can be made out of the direct coupling of processing performance and I/O bandwidth. The purpose of the FMC specification is to allow one or more FPGAs on a host card to connect directly with the I/O devices on the mezzanine module - just as if the device were on the host board. Busses like PCI-X are redundant and would get in the way of the FPGA and its I/O devices. This intimacy means the interface can be optimal and savings can be made in real estate, cost and power - with boosted bandwidth and reduced latency.

An FMC is similar in height and width to a PMC, but almost half the length. The reduced width, compared with PMC or XMC, enables up to three FMCs to be fitted to a 6U host. The FMC specification has a default stacking height of 10 mm, but also permits a stacking height down to 8.5 for low-profile solutions. The majority of FMC host/carriers use VPX (3U and 6U), VXS and AMC formats, but there are also PCI Express solutions such as the Xilinx ML605 Virtex-6 evaluation card. The FMC specification provides for a large number of differential connections, up to 80 pairs, (or 160 single-ended signals), to support one or more high speed parallel interfaces between the FPGA and I/O devices. There are also a number of serial connections (up to ten pairs) suitable for multi-gigabit transceivers (MGTs) operating up to 10 Gbytes/s. FMC modules and hosts support two connector options; a low-pin-count (LPC) 160-pin connector and a high-pin-count (HPC) 400-pin connector. The majority of FMC solutions are likely to use the HPC variant. Although aimed at I/O, FMCs can be used for any function that might connect to an FPGA including DSPs, memory or even another FPGA.

Connectivity for FMC modules is unusual in that the number of active connections is not defined, only the upper limit. This means that host carriers need not provide the same number of FPGA signals as another host. To fully populate an HPC solution may require a large FPGA, so reduced pin-out offers cost sensitivity. This is something to be aware of, but the specification defines that the signals populate the LPC or HPC connector at a given position and add to the connector in a given sequence such that if two hosts provide x signal, they will use the same connector pins.

When it comes to power supply requirements, the FMC specification has a neat trick: the host detects what the FMC power should be and the host provides it. This is achieved through the host interrogating the FMC E2PROM and an adjustable power supply. The benefit to the FMC is a simplified power requirement thereby freeing up valuable real estate for more I/O. Although around half the PWB area of an XMC, the FMC can sometimes achieve greater I/O functionality, most notably for rugged applications. If the solution requires a large FPGA and if the XMC module complies with the VITA 20 specification, there are restrictions as to where the FPGA can be located. In turn, this may limit the available area to fit the I/O devices. Let us consider an actual example with a pair of designs using the same I/O devices for a rugged application; one using an XMC format card and one using an FMC format card. Because the rugged XMC specification requires an area across the middle of the board to mate up with a host-stiffening bar (which doubles as a primary thermal interface conduction-cooled variant), a large FPGA (for example 35mm x 35mm) invariably needs to be fitted to the area of the circuit board closest to the front panel, and just where the design would want to fit the I/O devices. The useful space in which to fit the I/O devices is perhaps a quarter of the overall real estate of the XMC and not very efficient. In comparison, the FMC even though it is around half the size of the XMC, has a far greater real estate area for the I/O devices. In this example, the FMC is able to support two ADCs for two 3GS/s channels compared to the single channel of the XMC. Of course an XMC using a smaller FPGA, or not restricted by the rugged XMC specification, may not be affected to such an extent, provided it still has a sufficient number of I/O connections to the devices. An FMC may be smaller, but it may still be able to support greater functionality than its larger XMC equivalent.

Jeremy Banks, ISR, embedded computing

Author’s Biography

Jeremy Banks

Product Marketing Manager, ISR Solutions

Jeremy Banks is a Product Marketing Manager for Sensor and I/O Processing in the ISR group at Curtiss-Wright. He has been involved in the defence embedded computing industry for over 25 years holding positions in engineering design, marketing and product management in DSP, Multi-Processing, RF IO, SBCs, FPGAs and System solutions. Jeremy is a graduate of the University of Surrey in Electronic and Electrical engineering.

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