Mastering the art and science of sample clock synchronization
August 29, 2016 | BY: Jeremy BanksDownload PDF
There are many aspects of analog digitization that affect the overall performance of a system. Native resolution of the ADC, sample clock jitter and noise are just a few examples, each becoming tougher the faster the sample speed. However, synchronization between each of the analog input channels can be critical too. Beamforming or direction finding applications rely on precise delay measurement between sensors to establish the direction of a threat. Misaligning or missing a sample directly manifests itself as an additional delay, resulting in an error in the perceived direction of the threat.
These errors appear small but at a spacing of around 10m between sensors and 3GSps, this translates to an error of around 0.1 degrees (15m error at 10km) – even before any other system errors are taken into account in separating the signal of interest from all the other signals being picked up from the antennas. For direction finding applications, better SDFR will allow the system to identify the emitter at greater distances, assuming the hostile radar is turned on. However, much of the usefulness is lost if the error in being able to establish the bearing is not appropriately accurate enough. In reality, DF system designers prefer sub-sample accuracy if it can be achieved at the sample speeds required. Beamforming is not the only type of application where synchronization between analog input channels is important; applications such as radar where dual inputs form the I and Q provided by front end tuners require synchronization as well.
FPGAs are the most practical devices to interface to high-speed ADC devices. However, the native sample speed of the fastest ADCs is faster than even the latest FPGA’s interface capability so these ADCs have multiplexed interfaces to present a wider, but slower digital interface. For many ADCs, the first valid sample from power on can be on any of the multiplexed lanes. In addition, the internal data pipeline can be deep within the ADC, so it can take quite a few sample clock cycles before “real” data is made available to the FPGA.
In short, establishing the alignment of valid data is not always straightforward and can be non-deterministic on a power cycle to power cycle basis. With that said, as fast ADCs run continuously, the data pipeline will be constant while the sample clock is continually supplied. Once invalid data is flushed and new data aligned, it will thereafter stay aligned. For some systems integrators, a strategy of calibrating this fixed analog input to digitized data on each power up is the way forward. For systems requiring maximum performance over a wide temperature range but just power on at the beginning of a mission, periodic recalibration is needed if there are wide changes in temperatures, though some ADCs are more tolerant of this than others.
When designing synchronization schemes with Curtiss-Wright Defense Solutions equipment, multiple strategies are used (especially for high sample rate data converters), and can represent where the majority of FPGA IP development is focused for any given project. A key step includes training the ADC and FPGA digital interfaces such that the optimum timing eye is established to best mitigate the need for recalibration over temperature. In addition, clock generators temporarily stop the sample clock to all ADCs to allow the FPGAs to align themselves and flush data pipelines including those within the FPGA IP and even between boards. When the sample clock is released, the ADCs will then run synchronously since only clocks slaved off a single master reference is used. Clock generators such as XCLK1, for example, do not use separate PLLs for each clock output but instead use low jitter phase matched clock distribution buffers. Since all sample clocks are controlled in this manner, the system is coherent.
The ADCs have additional feature such as trigger inputs which use the LSB output to signal the first sample to pass through the data pipeline. This helps ensure all samples are cycle accurate, and the common reference clock ensures that, subject to length matched cables, the samples are sub-sample clock accurate.
- Synchronization requires careful system design down to the board level – especially over temperature
- Sample clock synchronization shouldn’t be taken for granted and can be the most challenging part of HDL development
- Sample clocked synchronization must be repeatable every time