AFED-424A 24 Channel Discrete Input Module With Programmable Counters, Time Tagging and High Bandwidth

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Key Features

  • 24 differential ended, discrete, bi-level input channels
  • 24 independent, 32-bit counters with ten different operating modes
  • 40 ns internal resolution
  • FIFO based time tagging
  • High bandwidth (1 MHz)
  • Detection of 0.5 μs wide input signal pulses

Applications

  • Engine speed measurement
  • Data capture from a parallel bus
  • Timestamping of events
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The AFED-424A monitors the status (high/low) of up to 24 differential ended discrete input channels. Each of these has an assigned programmable 32-bit counter. Additionally each of the inputs can be used to trigger time tagged events.

Each counter can be programmed to operate in one of the following modes: Period, Pulse Width, Duty Cycle, Frequency, Events Since Sample, Events Since Power Up, Events Since Trigger, Samples Since Power Up, Samples Since Event, or Time Since Event. The range of each counter is programmable, as is the threshold (within ±28V), hysteresis (0.8 to 20V) and sensitivity to the rising/falling edge.

All the channels control the time tagging to the 1K word deep FIFO (96 bits wide each word). For each input, time tagging can be triggered by a rising edge, falling edge, both edges, or neither (when the channel is disabled). Every time a trigger occurs, a 96-bit word is written to the FIFO consisting of the 24 inputs (configurable to be either input state after the change or value representing the bits which triggered the event) and the 64-bit time at which the event happened. You can choose to store up to 60 bits IRIG time or 64-bit IEEE 1588-2004 Precision Time Protocol version 1 (PTPv1) time in the FIFO. There are also three FIFO flags which indicate that the FIFO is empty, that a message has been skipped, or that a message is stale.

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