AXN/DSI/401 - 24 Channel Discrete Input

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Features

  • 24 differential ended, discrete, bi-level input channels
  • 24 independent, 32-bit counters with ten different operating modes
  • 40 ns internal resolution
  • FIFO based time tagging
  • Resettable counters
  • Detection of 0.5 μs wide input signal pulses

Applications

  • Engine speed measurement
  • Data capture from a parallel bus
  • Timestamping of events
AXN/ITE/01U - Remote housing for Axon module

AXN/ITE/01U - Remote housing for Axon module

The Axonite (AXN/ITE/01U) houses one Axon user module . It allows the user modules to be housed remotely from the Axon chassis so modules can be located closer to sensors, which can improve the...

AXN/EXT/401 - Axon extender card

AXN/EXT/401 - Axon Extender Card

The AXN/EXT/401 is an extender card, which allows a module contained in an Axonite (AXN/ITE/01U) remote housing to connect to an Axon chassis. Axonites allow modules to be separated from the...

Flexible ADC Module

AXN/ADC/401 - Flexible ADC Module - 8 analog channels

The AXN/ADC/401 is used to condition and digitize up to eight analog channels. Each channel can be configured for use in differential ended or single ended voltage measurement, AC coupled single...

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Programmable Counters, Time Tagging

The AXN/DSI/401 is an Axon bus monitoring module that monitors the status (high/low) of up to 24 differential ended discrete input channels. Each of these has an assigned programmable 32-bit counter. Additionally each of the inputs can be used to trigger time tagged events.

Each counter can be programmed to operate in one of the following modes: Period, Pulse Width, Duty Cycle, Frequency, Events Since Sample, Events Since Power Up, Events Since Trigger, Samples Since Power Up, Samples Since Reset, or Time Since Event. The range of each counter is programmable, as is the threshold (within ±28V), hysteresis (0.8 to 20V) and sensitivity to the rising/falling edge.

All the channels control the time tagging to the 1K word deep FIFO (80 bits wide each word). For each input, time tagging can be triggered by a rising edge, falling edge, both edges, or neither (when the channel is disabled). Every time a trigger occurs, a 96-bit word is written to the FIFO consisting of the 24 inputs (configurable to be either input state after the change or value representing the bits which triggered the event) and the 64-bit at which the event happened. You can choose to store 48-bit IRIG 106 Chapter 4 time or 64-bit PTP time in the FIFO. There are also three FIFO flags which indicate that the FIFO is empty, that a message has been skipped, or that a message is stale.

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